The present invention relates generally to semiconductor devices and more specifically to methods of fabricating copper vias having improved electromigration (EM) resistance.
With the shrinking of dimensions, or design rule, in semiconductor devices, a greater challenge is occurring in copper (Cu) via electromigration (EM).
U.S. Pat. No. 6,096,648 to Lopatin et al. describes a copper damascene process with an impurity, e.g. Mg, implanted into copper lines to form a doped copper line interconnect. The implanted ions are activated by a subsequent annealing or deposited step that requires an elevated temperature.
Copper alloy, e.g. CuMg xcx9c2% and CuAl xcx9c1% with a resistivity of xcx9c2 xcexcOhm-cm), has been widely studied to improve Cu line performance against Cu oxidation by the self-passivation layer formation, i.e. e.g. MgO or Al2O3, respectively, at the copper surface which also improves EM.
For example, U.S. Pat. No. 6,057,223 to Lanford et al. describes a copper damascene process by: forming a metal layer on the surface of a microelectronics substrate; forming a copper layer upon the metal layer; and annealing the metal and copper layers which diffuses at least some of the metal layer through the copper layer to the surface of the copper layer where the diffused metal ions forms a protective metal oxide at the surface of the copper layer.
U.S. Pat. No. 6,022,808 to Nogami et al. describes a doped copper damascene process. A via/contact hole and/or trench formed within a dielectric layer is filled with undoped copper. A doped (e.g. Pd, Zr, or Sn) copper layer is deposited on the undoped copper via/contact hole and/or line and the structure is annealed to diffuse the dopant from the overlying doped copper layer into the copper via/contact hole and/or line to improve its electomigration resistance.
Accordingly, it is an object of the present invention to provide a method to improve Cu via EM resistance.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a semiconductor structure having an exposed metal interconnect structure therein is provided. The metal interconnect structure including a metal via portion. A capping layer is formed over the metal interconnect structure. A via pattern structure is formed over the capping layer. The via pattern structure having a via pattern hole aligned with the metal via portion of the metal interconnect structure. Ions are implanted through the via pattern hole into the metal via portion, and any portion of the metal interconnect structure above the metal via portion. Whereby the metal via portion and the portion of the metal interconnect structure above the metal via portion have improved electromigration resistance.